The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Memory integrated circuits (ICs) comprise memory arrays. The memory arrays include memory cells arranged in rows and columns. The memory cells may include cells of volatile or nonvolatile memory. Volatile memory loses data stored in the memory cells when power is removed from the memory cells. Nonvolatile memory retains data stored in the memory cells when power is removed from the memory cells.
The memory cells in the rows and columns of a memory array are addressed by word lines (WLs) that select the rows and bit lines (BLs) that select the columns. The memory ICs comprise WL and BL decoders that select the WLs and BLs, respectively, during read/write (RAW) and erase/program (EP) operations.
Referring now to FIG. 1, a memory IC 10 comprises a memory array 12, a WL decoder 16, a BL decoder 18, and a control module 19. The memory array 12 comprises memory cells 14 arranged in rows and columns as shown. The WL and BL decoders 16, 18 select the WLs and BLs, respectively, depending on the addresses of the memory cells 14 selected during RAN and EP operations.
The control module 19 receives commands (e.g., read, write, erase, program, etc.) from a host (not shown). The control module 19 reads and writes data in the selected memory cells 14. Additionally, the control module 19 erases and programs the selected memory cells 14 when the memory cells 14 include cells of nonvolatile memory such as flash memory.
For example only, the memory cells 14 may include cells of NAND or NOR flash memory. Each memory cell 14 may be programmed to store N binary digits (bits) of information, where N is an integer greater than or equal to 1. Accordingly, each memory cell 14 may have 2N states. To store N bits per cell, each memory cell 14 may comprise a transistor having 2N programmable threshold voltages (hereinafter threshold voltages). The 2N threshold voltages of the transistor represent the 2N states of the memory cell 14, respectively.
Referring now to FIG. 2, a memory cell 14-i may comprise a transistor 50 having a threshold voltage VT. The transistor 50 may comprise a floating gate G (hereinafter gate G), a source S, and a drain D. The amount of charge stored in the gate G during a write operation determines the value of threshold voltage VT and the state of the memory cell 14-i. 
For example only, the transistor 50 may have two programmable threshold voltages VT1 and VT2 depending on the amount of charge stored in the gate G. When the amount of charge stored in the gate G is Q1, the threshold voltage of the transistor 50 is VT1. When the amount of charge stored in the gate G is Q2, the threshold voltage of the transistor 50 is VT2. Depending on the amount charge stored in the gate G, a gate voltage (i.e., VGS) having a value greater than or equal to VT1 or VT2 may turn on the transistor 50 (i.e., generate the predetermined drain current).
The state of the memory cell 14 (i.e., data stored in the memory cell 14) is read by measuring the threshold voltage VT of the transistor 50. The threshold voltage VT is measured by applying the gate voltage to the gate G and sensing the drain current. The drain current is sensed by applying a small voltage across the source S and the drain D of the transistor 50.
When the gate voltage is less than the threshold voltage VT, the transistor 50 is off, and the drain current is low (approximately zero). When, however, the gate voltage is greater than or equal to the threshold voltage VT, the transistor 50 turns on, and the drain current becomes high (i.e., equal to the predetermined drain current corresponding to the VT). The value of the gate voltage that generates the high drain current represents the threshold voltage VT of the transistor 50.
Typically, states of memory cells in a block or a page of a memory array are sensed at a time. The gates of the transistors of the memory cells in the block are connected to a WL. The WL is selected, and a voltage is applied to the WL. The states of N-bit memory cells are sensed by stepping through (2N−1) voltages on the WL and determining the threshold voltages of the transistors when the drain currents of the transistors first exceed a predetermined (preprogrammed) value.
Referring now to FIGS. 3A and 3B, the threshold voltage of the transistor 50 is measured as follows. For example only, the transistor 50 may have one of four threshold voltages VT1 to VT4, where VT1<VT2<VT3<VT4. Accordingly, the memory cell 14-i may have one of four states 00, 01, 10, and 11.
In FIG. 3A, the control module 19 comprises a voltage generator 20 and current sensing amplifiers 22. The voltage generator 20 and the current sensing amplifiers 22 may be collectively called a read module. The number of current sensing amplifiers is equal to the number of BLs. For example, when the IC 10 comprises B BLs, the current sensing amplifiers 22 include B current sensing amplifiers for B BLs, respectively, where B is an integer greater than 1.
In FIG. 3B, the WL decoder 16 selects a WL comprising memory cells 14-1, 14-2, . . . , 14-i, . . . , and 14-n (collectively memory cells 14) when the states of the memory cells are to be determined. Each of the memory cells 14 includes a transistor similar to the transistor 50. The transistors are shown as capacitances C that store the charge in the gates.
When a read operation begins, the voltage generator 20 supplies a voltage (e.g., a staircase voltage) to the WL decoder 16. The WL decoder 16 inputs the voltage to the selected WL. Accordingly, the voltage is applied to the gates of the transistors on the selected WL.
The current sensing amplifiers 22 include one current sensing amplifier for each BL. For example, a current sensing amplifier 22-i communicates with a bit line BL-i and senses the drain current that flows through the transistor 50 of the memory cell 14-i. The current sensing amplifier 22-i senses the drain current by applying a small voltage across the source and the drain of the transistor 50.
Each current sensing amplifier senses the drain current that flows through the respective one of the transistors of the memory cells 14. The control module 19 measures the threshold voltages of the transistors based on the drain currents sensed by the respective current sensing amplifiers 22.